The present invention relates generally to the manufacture of integrated circuits (ICs). More specifically, the invention relates to a method of manufacturing self aligned buried plates within a deep trench formed into a silicon substrate.
Buried plate structures formed within deep trenches that are etched into a silicon substrate are commonly used in the integrated circuit industry. These buried plate structures may be used to, for example, form integrated circuit components such as trench capacitors that may be used as memory storage nodes in devices such as DRAMs. However, the conventional vertical patterning processes used to produce these buried plates are relatively complex and, as described in more detail below, are not self-aligning. In order to more clearly illustrate these problems, a prior art process for producing a trench capacitor on a silicon wafer will be described with reference to FIGS. 1-19.
As indicated in FIG. 1, a silicon wafer 100 is provided having a deep trench 102 etched into wafer 100. Wafer 100 typically has a thin pad oxide layer 104 and a pad nitride layer 106 formed on a top surface 108 of a silicon substrate 110. As is known in the art, pad oxide layer 104 acts as a stress relieving layer for preventing pad nitride layer 106 from separating from silicon substrate 110 during subsequent high temperature process steps. Pad nitride layer 106, which is typically about 200 angstroms thick, acts as a protective layer for top surface 108 of substrate 110 during subsequent process steps such as oxidation steps.
Although not illustrated in the figures, trench 102 is formed into wafer 100 using a deep trench etching process. To accomplish this, a Borosilicate glass (BSG) hard mask layer 112 is applied over pad nitride layer 106. BSG hard mask 112 is then patterned with a resist material (not shown) and etched using a conventional hard mask etching process such as a dry etch process using an CF4/CF3/Argon etchant. One or more etching process opens BSG hard mask layer 112 (as well as pad nitride layer 106 and pad oxide layer 104) in the areas above where deep trench 102 is to be etched. The resist material (not shown) used to pattern hard mask 112 is then removed using well known resist removing processes. Deep trench 102 is then etched using an appropriate etching process such as a dry etch using an HBr/NH3/O2 etchant. In this case, the deep trench is etched to a level of about 8 microns below top surface 108 of silicon substrate 110 forming trench sidewalls 114 and 116.
As illustrated in FIG. 2, once trench 102 is etched into wafer 100, BSG hard mask layer 112 is removed using any conventional hard mask removal process such as, for example, a vapor phase etching process using HF vapor. At this point, the process steps used to form a buried plate structure within the deep trench begins.
Referring to FIG. 3, the first step in actually forming a conventional buried plate structure involves depositing an arsenic doped silicon tetraethylorthosilicate glass (ASG TEOS) layer 118 over pad nitride layer 106 and over the surfaces of trench 102. As described in more detail hereinafter, ASG TEOS layer 118 is used to provide the arsenic doping for certain regions of silicon substrate 100 during subsequent annealing steps. This layer may be applied using a conventional chemical vapor deposition (CVD) technique and is typically applied at a thickness of, for example, about 40-60 nm.
Once ASG TEOS layer 118 has been applied, it is etched from the top surface of the pad nitride layer and from certain uppermost portions of trench sidewalls 114 and 116 of trench 102. This etching process is accomplished using the process steps illustrated in FIGS. 4-7.
As illustrated in FIG. 4, a resist material 120 is first applied to wafer 100. This resist material fills trench 102 and coats the top surface of wafer 100 with a layer of resist material. Next, as shown in FIG. 5, resist material 120 is recessed or etched back to a desired level within trench 102, in this case, to a level in the range of about 5.5 to 6.5 microns above the bottom of trench 102. This etching back of the resist exposes portions of the ASG TEOS layer at the uppermost portions of the sidewalls 114 and 116 of trench 102. This step is accomplished using a conventional photoresist etching process. As described in more detail hereinafter, this is the step that determines the level of the first vertical patterning step for this process.
Once resist material 120 has been etched back to the desired level, ASG TEOS layer 118 is etched away from the top of wafer 100 and from the exposed portions of sidewalls 114 and 116. A wet etching process using, for example, a BHF etchant is typically used to etch, and slightly over etch, the ASG TEOS layer. After this etching step, ASG TEOS layer 118 may be slightly recessed below the level of the remaining resist as shown in FIG. 6. And finally, this etching process is finished by removing the remaining portions of resist material 120 using a conventional photoresist removal process. Once the resist is removed, only portions of ASG TEOS layer 118 remain with these portions covering the bottom portions of trench 102.
Once the etching process for the ASG TEOS layer is complete, the ASG TEOS layer is annealed as illustrated in FIGS. 8-10. This annealing process produces an arsenic doped region within silicon substrate 110 surrounding the bottom portions of trench 102. This arsenic doped region forms the buried plate structure. In the specific case of a trench capacitor that is being described, this arsenic doped region forms one of the plates of the capacitor.
Prior to the actual annealing step, a cap TEOS layer 122 is deposited over wafer 100 coating trench 102 as illustrated in FIG. 8. Cap TEOS layer 122 is an undoped TEOS or ozone TEOS layer that prevents the arsenic doped TEOS 118 from doping the upper portions of trench sidewalls 114 and 116 and/or to prevent the arsenic dopant from escaping from the trench during the dopant drive anneal step. Cap TEOS layer 122 is applied using a conventional CVD technique and is typically applied at a thickness of, for example, about 400 Angstroms.
After cap TEOS layer 122 is applied, wafer 100 is annealed. During the annealing step, the temperature is elevated for an specific length of time. In this specific case, the temperature is raised to about 1050 degrees F. for a period of about 30 minutes. This high temperature moves the arsenic from ASG TEOS layer 118 into the surrounding region of silicon substrate 110 thereby forming a buried plate structure 124 within a region of silicon substrate 110 surrounding the bottom portion of trench 102. This process is illustrated in FIG. 9. After the annealing step, the remaining portions of ASG TEOS layer 118 and cap TEOS layer 122 are removed. This is accomplished using a conventional process such as, for example a wet etching process using, for example, a BHF etchant.
Once buried plate structure 124 is formed as described above, a nitride layer is formed on the trench walls adjacent to buried plate structure 124 using the process steps illustrated in FIGS. 11-15. This nitride layer acts as a dielectric for the trench capacitor. This process of forming the capacitor dielectric is the second vertical patterning step of the overall process of forming the trench capacitor. As will be described in more detail hereinafter, this second vertical patterning step must be strictly controlled so that the top of the nitride layer is at the proper level relative to buried plate structure 124. Because two separate vertical patterning steps are used to locate the top of the nitride layer relative to the top of buried plate structure 124, these layers are not self-aligned.
Referring now to FIG. 11, the process of forming the capacitor dielectric will be described. As shown in FIG. 11, a nitride layer 126 is deposited over wafer 100 coating trench sidewalls 114 and 116. Nitride layer 126 is formed using a conventional low pressure chemical vapor deposition process and is about, for example, 7 nm thick. In order to improve the quality of nitride layer 126, nitride layer 126 may be reoxidized at this stage using a wet oxidation process. This reoxidizing step reduces any defects in nitride layer 126 by filling any holes with oxide and improves the dielectric properties of nitride layer 126.
Next, an arsenic doped polysilicon material 128 is applied over wafer 100 so that it fills trench 102 as illustrated in FIG. 12. Arsenic doped polysilicon material 128 is typically formed using a layering process in which a layer of undoped polysilicon is laid down, then a layer of arsenic, and then another layer of undoped polysilicon in order to form overall layer 128. These alternating layers, which are not shown in the Figures, are mixed in subsequent high temperature oxide forming steps. After overall arsenic doped polysilicon material 128 is laid down, a conventional planarization step such as chemical-mechanical polish (CMP) is performed which removes polysilicon material 128 from the top surface of wafer 100.
At this point, polysilicon material 128 is recessed or etched to a desired level within trench 102. Polysilicon material 128 is typically etched using a conventional dry etch process such as a reactive ion etching process using SF6 as the reactant. As described briefly above, this etching step is very important because it determines the vertical alignment of the nitride layer relative to the previously formed buried plate structure 124. Therefore, it is critical that this etch process removes the polysilicon material 128 down to a level just slightly below the level of the top of buried plate structure 124 as illustrated in FIG. 14. For example, in this case, the polysilicon material is etched down to a level of about 100 nm below the uppermost portion of the buried plate structure 124. If these two vertically positioned layers are not properly aligned, the trench capacitor may not be able to hold its charge properly resulting in a defective memory cell.
After polysilicon material 128 is etched to the proper level, nitride layer 126 and any exposed reoxidized nitride are etched away from the top surface of wafer 100 and from the uppermost portions of trench sidewalls 114 and 116 as illustrated in FIG. 15. This step uses a conventional nitride etching process such as, for example, a wet etch process using, for example, an HF-glycerol etchant. This nitride etching step exposes silicon substrate 100 at the uppermost portions of trench sidewalls 114 and 116 and completes the process of forming the nitride dielectric layer for the trench capacitor.
The next process involved in forming the trench capacitor is the process of forming a protective oxide layer on the exposed uppermost portions of trench sidewalls 114 and 116. In this case, the protective oxide layer is a two layer structure formed using the steps shown in FIGS. 16-18. The protective oxide layer is used to cover the exposed silicon substrate 100 at the uppermost portions of trench sidewalls 114 and 116, cover the exposed edge of nitride layer 126, and isolate the buried plate structure 124 from the arsenic doped polysilicon 128 which is already in trench 102 as well as additional arsenic doped polysilicon material that will be added in a subsequent process step. Additionally, the high temperature steps associated with forming the protective oxide layer are used to mix the arsenic doped polysilicon material 128.
Referring initial to FIG. 16, the first step in forming the protective oxide layer involves performing a collar oxide forming step. This is done using a conventional collar oxidation process such as a dry oxidation process to form a thin collar oxide layer 130. Collar oxide layer 130 is formed on the exposed uppermost trench sidewalls 114 and 116. However, since the top surface of polysilicon material 128 is also exposed during the collar oxidizing step, collar oxide layer 130 is also formed over the top of polysilicon material 128 as illustrated in FIG. 16. In this case, collar oxide layer 130 is formed to be about 8 nm thick on trench sidewalls 114 and 116. Also, since the collar oxidation step is a high temperature step, this step begins to mix the arsenic and polysilicon making up arsenic doped polysilicon material 128.
After collar oxide layer 130 is formed, an additional collar oxide deposition layer 132 of collar oxide is deposited over wafer 100 such that it coats the unfilled portions of trench 102 as illustrated in FIG. 17. In this case, collar oxide deposition layer 132 is deposited at a thickness ranging from about 30 nm to about 45 nm. The thickness varies depending on the location on wafer 100 because of the varying contours of the wafer. For example, collar oxide deposition layer 132 may be about 45 nm thick on the top surface of wafer 100 and about 30 nm thick on trench sidewalls 114 and 116. Collar oxide deposition layer 132 is applied using a conventional collar oxide deposition process such as a plasma enhanced TEOS process. In this case, this step includes a 20 minute anneal at a temperature of about 1000 degrees F. This anneal step typically slightly thins collar oxide layer 132. As mentioned above for the high temperature collar oxidizing step, this high temperature anneal step further mixes the arsenic and the polysilicon that makes up arsenic doped polysilicon material 128.
The final step in forming the protective oxide layer is illustrated in FIG. 18. This step involves etching away the collar oxide layers from the top of polysilicon material 128 and the top of wafer 100. A conventional oxide etching, process such as a dry etch process using a CHF3/He/O2 etchant is used to etch the collar oxide layers. This etching step is important because it is critical to make sure that substantially all of the collar oxide layers 130 and 132 are removed from the top of polysilicon material 128 within trench 102. If all of the collar oxide material is not removed, it may cause electrical resistance between the arsenic doped polysilicon material 128 in the bottom of trench 102 and the arsenic doped polysilicon material that is placed over the top of material 128 as described immediately below. This electrical resistance may interfere with the proper functioning of the trench capacitor.
Once the protective oxide layers are formed on uppermost trench sidewalls 114 and 116, the final step in forming the trench capacitor is the step of applying another layer of arsenic doped polysilicon material 134 such that it fills the remaining unfilled portions of trench 102 as illustrated in FIG. 19. Arsenic doped polysilicon layer 134 may be applied in the same multi-layer manner as described above for arsenic doped polysilicon material 128. If this is the case, the arsenic and the polysilicon would be mixed in subsequent process steps that will not be described herein.
The above described process results in a trench capacitor made up of a buried plate structure 124, a nitride dielectric layer 126, and arsenic doped polysilicon material 128 which acts as the second plate of the capacitor. Arsenic doped polysilicon material 134 provides an electrical path for charging the second plate formed by material 128. Although this overall process results in a useful trench capacitor, there are several disadvantages associated with the above described prior art process.
First, as mentioned above, there are two vertical patterning steps which determine the vertical positioning of the various elements of the capacitor. The first vertical patterning step is illustrated best in FIG. 5. This step determines the height within the trench at which the top of the buried plate structure 124 will be located. The second vertical patterning step is best illustrated in FIG. 14. This is the step which determines the height within the trench at which the top of nitride dielectric layer 126 will be located. This step also determines the height within the trench at which the bottom edge of the protective oxide layers 130 and 132 will be vertically located. Because the vertical location of the top of the buried plate structure 124 and the vertical location of the top of the nitride layer 126 are determined in two separate process steps, this overall process is not self-aligning. That is, these two vertical patterning steps must be very closely controlled to insure that theses two layers are properly aligned. This is a difficult process and results in a high cost for producing trench capacitors using this approach. If these vertical layers are not properly aligned, the capacitor may not be able to properly hold its charge resulting in a defective capacitor.
As another disadvantage, the above described process is a complex process including a large number of individual process steps. This large number of steps in itself makes the process expensive and time consuming. For example, the above described process includes multiple high temperature anneal steps. These steps consumes more of the available temperature budget, are time consuming and therefore reduce the throughput of the manufacturing process making the process more costly.
Additionally, as mentioned above, the collar oxide step is important because it is critical to make sure that substantially all of the collar oxide layers 130 and 132 are removed from the top of polysilicon material 128 within trench 102. If all of the collar oxide material is not removed, it may cause electrical resistance problems between the arsenic doped polysilicon material 128 in the bottom of trench 102 and the arsenic doped polysilicon material 134 that is placed over the top of material 128. This electrical resistance may interfere with the proper functioning of the trench capacitor. In order to ensure the proper etching of these collar oxide layers, the top surface of polysilicon material 128 on which the oxide layers are formed should be as level or flat as possible. If there is a substantial concave or V shape to this top surface, the thickness of the collar oxide layers may vary dramatically making it difficult to properly etch all of the collar oxide material from the top surface of polysilicon material 128.
In order to provide a level, flat surface on the top of polysilicon material 128, deep trench 102 may be formed with slightly tapered trench sidewalls. That is, trench 102 is wider at the top of the trench and narrower at the bottom of the trench. This helps ensure that the etching process used to etch back polysilicon material 128 results in a flat and level top surface for the remaining polysilicon material 128. Unfortunately, the use of a tapered trench with a narrower bottom than top causes the capacitance of the trench capacitor formed using the above described process to be less than the capacitance that would be possible if trenches having vertical sidewalls were used.
In view of the foregoing, it is desirable to provide a process for producing a trench capacitor that reduces or eliminates the above described problems associated with the prior art process.
As will be described in more detail hereinafter, a method of forming a buried plate in a silicon substrate having a deep trench etched into the silicon substrate is herein disclosed. The trench has sidewalls defining the depth of the trench. The method includes the step of forming a highly doped polysilicon layer within the trench. A nitride layer is then formed within the trench over the polysilicon layer. After forming both the polysilicon layer and the nitride layer, both the polysilicon layer and the nitride layer are etched from a certain uppermost portion of the sidewalls of the trench thereby exposing the silicon substrate at the uppermost portions of the sidewalls. After exposing the silicon substrate at the uppermost portions of the sidewalls, a collar oxide layer is formed over the exposed silicon substrate at the uppermost portions of the sidewalls thereby protecting any edges of the polysilicon layer exposed by the etching step.
In one embodiment, the method further includes the step of forming a thin thermal oxide layer within the trench prior to forming the highly doped polysilicon layer. In a specific version of this embodiment, the thin thermal oxide layer is approximately about 15 angstroms thick.
In another embodiment, the highly doped polysilicon layer is doped with arsenic. Preferably, the concentration of the arsenic in the polysilicon layer is greater than about 5E19/cm3, the polysilicon layer is approximately about 300 angstroms thick, and the polysilicon layer is formed using a chemical vapor deposition process. For this embodiment, the nitride layer is approximately about 6 nm thick and the nitride layer is formed using a low pressure chemical vapor deposition process.
In another embodiment which includes the thermal oxide layer, the step of etching the polysilicon layer and the nitride layer includes several steps. Before etching the polysilicon layer and the nitride layer, the trench is filled with a resist material. The resist material is then recessed to a certain level within the trench. The nitride layer and the polysilicon layer are then etched with the thermal oxide layer acting as an etch stop. The thermal oxide layer is then etched to expose the silicon substrate at the uppermost portions of the sidewalls of the trench. And finally, any remaining resist material is removed from the trench. In one version of this embodiment, the trench is formed approximately about 8 microns deep within the silicon substrate and the resist material is recessed to a level of approximately about 5.5 to 6.5 microns above the bottom of the trench.
In another embodiment, the method is used to form a trench capacitor in a silicon substrate for use in a DRAM device. In this embodiment, the portions of the polysilicon layer that remain after the etching step are used to form a buried plate forming part of the trench capacitor. The portions of the nitride layer that remain after the etching step are used to form a dielectric layer for the trench capacitor. In this embodiment, the trench is filed with doped polysilicon after the step of forming the collar oxide. Portions of the doped polysilicon fill act as a second plate for the trench capacitor.